The present invention generally relates to a system and method for providing PCI power management support without requiring a clock. More specifically, the invention is related to an integrated circuit which is capable of detecting events external to a computer, while the computer""s clock is sleeping, and thereafter, internally signaling to the computer""s operating system to wake up the computer system in order to provide for the external event.
With the advancement of technology has come an increase in the complexity of computer systems along with greater demands on the required performance of clocks internal to computers. Minimum clock speed requirements for computers have increased dramatically due to the ever-present need for faster computation. Unfortunately, internal clocks use a vast amount of power during computer use that is attributed to such things as data sampling. Also, an increase in computer clock speed results in even greater power use.
As a solution to the aforementioned power expenditure problem, computer systems implement power management systems to provide energy savings. Typically, the amount of power consumed by a computer is proportional to the frequency of an internal clock, which sequences the operation of various internal components. For example, one particular component may be a central processing unit (CPU) that may perform various tasks. These tasks may include spending a large percentage of time in idle loops, waiting for input/output operations to be completed, waiting for operator input, etc. To reduce power consumption, most power management systems concentrate on reducing CPU clock speed during periods of module inactivity and during periods wherein operations performed by the modules do not require high frequencies.
Additionally, there are times during which a computer system may not be actively used, or is not actively performing a useful function. During such times, transitioning the computer system to a sleep state, or low power consumption state, helps to preserve power, while having minimum impact on the performance of the computer system.
In order to implement power management systems, some computers or computer control devices include power management software that determines when a device or system meets a predefined inactivity level. After it has been determined that the predefined inactivity level has been exceeded, the software powers down the system, either partially or fully. For instance, the predefined inactivity level might be defined as an absence of application program execution and an absence of the receipt of external event signals for a specified period of time (e.g., key strokes or mouse movement signals from a user interface, or change in the status of another device that is being monitored by the system in question, such as a peripheral device attached to the computer via a PCI slot). This manner of powering down a device when the power management software detects the predefined inactivity level may vary greatly from system to system.
In some devices, power savings may be accomplished by saving the current system context in stable storage (e.g., battery backed random access memory (RAM)), and then powering down all components of the computer system other than the RAM and the components used to detect external event signals. In other systems, especially systems where vast response to external signals is deemed to be especially important, power usage is reduced without fully powering down components most likely to be needed for responding to the external signals. Instead, for systems where vast response to external signals is deemed to be especially important, the rate of clock signals may be reduced. As an example, reducing the rate of the clock signal delivery to a data processor (i.e., CPU) greatly reduces the power consumed by the data processor, while still allowing the data processor to continue performing background tests that use a small fraction of the computer system""s data processing capacity. When a qualifying external signal (i.e., one that requires restoring the system to full power) is detected, the power management software changes the rate of the clock signal delivered to the data processor back to its full, and normal rate.
Unfortunately, the aforementioned power management systems generally require a clock to be present to perform power management operation. Typically, the clock drives memory elements that store information for operating system usage.
In light of the foregoing, the invention is a system and method for providing PCI power management support without requiring a clock. The invention allows a computer to reside in a sleep mode and receive a power management event signal from an attached peripheral device in response to an external action request from an external source, thereby waking the computer and initializing device drivers to allow the peripheral device to perform predefined functions.
During initiation of the power management system, the system provides a peripheral device, which is attached to the computer, with a PME_Status bit. Upon occurrence of an external event, the peripheral device receives an external action request from the source of the external event. The peripheral device then sets the PME_Status bit and transmits a power management event (PME) signal to a computer operating system. Upon receiving the PME signal, the computer returns to a fully activated state. The computer operating system then searches all peripheral devices connected to the computer for the set PME_Status bit. Upon finding the source of the PME_Status bit, the computer initializes a device driver, which is related to the peripheral device, thereby allowing the peripheral device to function accordingly and accommodate the external action request.
The invention has numerous advantages, a few of which are delineated hereafter as examples. Note that the embodiments of the invention, which are described herein, possess one or more, but not necessarily all, of the advantages set out hereafter.
One advantage of the invention is that implementation merely requires minimal cost due to the use of very basic memory elements.
Another advantage is that it reduces global power dissipation of a circuit needed for power management support.
Other features and advantages of the present invention will become apparent to one of reasonable skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention as defined by the claims.